TWO DAYS full of events
Workshop Schedule
Below is the 2025 RISC-V in Space Workshop Schedule
Wednesday
April 2nd, 2025
7.30 – 8.30 am
Registration & Poster Setup
8.30 – 9.00 am
Welcome
08.30 CHAIRMAN’S WELCOME
Sandi Habinc – Frontgrade Gaisler
08.35 TECHNICAL CHAIR’S WELCOME
Roland Weigand – European Space Agency
08.40 LORD MAYOR’S WELCOME
Margareta Broang – City of Gothenburg
08.50 WELCOME TO SWEDEN
Dr. Ella Carlsson – Swedish National Space Agency
9.00 – 10.20 am
session – RISC-V IP CORES
09.00 KEYNOTE – Benefits the RISC-V Architecture can Bring to the Space Ecosystem
Andrea Gallo – RISC-V International
09.30 RVMC/NOEL3 – A new RISC-V Microcontroller CPU Core
Alfonso Carballo Boullosa – Frontgrade Gaisler
09.45 RISC-V Core for Space Microcontroller Applications in Airbus Crisa
Juan Antonio Ortega Ruiz – Airbus Crisa
10.00 PLATINUM SPONSOR – Challenges of New Space Platforms
Lorne Graves – Frontgrade Technologies
10.20 – 11.00 am
COFFEE, POSTERS & EXHIBITION
11.00 – 12.45 pm
session – ai oriented developments
11.00 KEYNOTE – Space Application – Leveraging FPGAs and RISC-V
Göran Bilski – AMD
11.30 The ISOLDE Space Demonstrator: A Platform for AI Applications on Satellites
Dr. Antonio Sciarappa – Leonardo
11.45 The METASAT Space Platform: High Performance On-Board Processing for Institutional Missions Using Multicores, GPU and AI Accelerator
Dr. Leonidas Kosmidis – Barcelona Supercomputing Center
12.00 Astral: a Mixed-Criticality RISC-V SoC Architecture for Satellite Onboard AI
Yvan Tortorella – Fondazione Chips-IT Italy
12.15 AI/ML for Space Applications on RISC-V: A Fully European Technology Stack Analysis
Dr. Pablo Ghiglino – Klepsydra Technologies
12.30 GOLD SPONSOR – The Future of Neuromorphic, event-based Processing in Space: What will the next generation Akida IP make possible
Alf Kuchenbuch – BrainChip Inc.
12.45 – 13.45 pm
lunch
13.45 – 15.20 pm
session – radiation and flight results
13.45 KEYNOTE – Open RISC-V Hardware in Space – One Small Step for Space, One Giant Leap for PULP
Dr. Frank Kagan Gurkaynak – ETH Zürich
14.15 Efficacy of Radiation Hardening by Design Techniques on an ASIC 32-bit RISC-V Microcontroller
Christopher Elash – University of Saskatchewan
14.30 SEE Characterization of NOEL-V on 28nm FD-SOI Platform for Space
Dr. Lucas Antunes Tambara – Frontgrade Gaisler
14.45 HARV – Hardened RISC-V System-on-Chip
Douglas Almeida dos Santos – University of Montpellier
15.00 SILVER SPONSOR – Develop your next RISC-V-based spacecraft with a digital twin in Renode
Piotr Zierhoffer – Antmicro
15.10 SILVER SPONSOR – Ensuring Ultra-reliable RISC-V Designs for Space
Adnan Hamid – Breker Verification Systems
15.20 – 16.00 pm
COFFEE, POSTERS & EXHIBITION
16.00 – 17.40 pm
session – Chip Implementations & Architectures
16.00 KEYNOTE – We have lift-off! The Past, Present and Future of RISC-V in Space
Ted Speers – Microchip Technology Inc.
16.30 DUROC Demonstrator in Radiation Hardened 7nm FinFET Technology
Dr. Alp Kilic – NanoXplore
16.45 High-Performance 64-bit HPSC Microprocessor (MPU) New Era of Autonomous Space Computing
Nicolas Ganry – Microchip France
17.00 GR765 – Octa-Core Rad-Hard Microprocessor
Magnus Hjorth – Frontgrade Gaisler
17.15 Akida: a Hardware Accelerator for AI Tasks, for Integration with RISC-V Systems
Dr. Douglas McLelland – BrainChip
17.30 SILVER SPONSOR – World’s First 50 TOPS RISC-V Modular and Upgradable AI Laptop for Advanced Space Systems Development
Yuning Liang – DeepComputing
18.00 – 21.30 pm
reception
dinner
18.00 DRINK
18.30 DINNER
Thursday
April 3rd, 2025
8.00 – 8.30 am
Registration
8.30 – 8.35 am
opening
08.30 TECHNICAL CHAIR
Roland Weigand – European Space Agency
8.35 – 10.20 am
session – Extensions, Fault Tolerance and Interconnects
08.35 KEYNOTE – RISC-V and EuroHPC – Powering Europe’s Future in High-Performance Computing
Dr. Alexandra Kourfali – EuroHPC Joint Undertaking
09.05 Fault-Tolerant RISC-V Softcore: SRAM-Based FPGA Implementation and Reliability Testing
Dr. Fernanda Kastensmidt – UFRGS University
09.20 Enhancing RISC-V Ecosystem for SEU-Resilient Inference on FPGA-Based Implementations
Giorgio Cora – Politecnico di Torino
09.35 Enhancing Cache Coherent Interconnects to Support Space Systems
Mehrzad Nejat – Chalmers University of Technology
09.50 Tightly-coupled VS Loosely-coupled Accelerators for Data Compression in Space Applications: a NOEL-V Study Case
Dr. Enrico Manfredi – Politecnico di Torino
10.05 GOLD SPONSOR – System Bus Access: Gaining Runtime Insights through the Debugger
Johannes Lask – SEGGER
10.20 – 11.00 am
COFFEE, POSTERS & EXHIBITION
11.00 – 12.45 pm
session – Security, Safety and Reliability
11.00 KEYNOTE – Take Back Control with RISC-V
Jimmy Le Rhun – Thales CortAIx Labs
11.30 Analysing Transient Execution Attacks Feasibility on the NOEL-V Platform
Gianluca Furano – European Space Agency
11.45 ENGAGE-V: A RERI-Compliant RISC-V Module for RAS in Space Applications
Prof. Daniele Rossi – University of Pisa
12.00 Flexible and secure payload integration; CDPU a RISC-V ’New Space’ approach
Dr. Gerard Rauwerda – Technolution B.V.
12.15 Enhancing Maintainability and Reliability in Space Applications: A RISC-V Based System Controller for High-Performance Data Processing Units for Small Satellites Using LiteX
Daniel Garbe – Fraunhofer EMI
12.30 GOLD SPONSOR – Full System Modeling and Simulation for RISC-V Platform Co-Design
John Leidel – Tactical Computing Labs
12.45 – 13.45 pm
lunch
13.45 – 15.45 pm
session – Software, Verification and Tools
13.45 KEYNOTE – All-in-one CPU, Vector and Tensor RISC-V Computing from Semidynamics
Dr. Roger Espasa – Semidynamics
14.15 Test-in-the-loop: Designing RISC-V Soft-Cores through Methodic Validation
Tijmen Smit – University of Twente
14.30 RISC-V Unified Database
Afonso Oliveira – Universidade do Minho / Synopsys, Inc.
14.45 Embracing Both Emulation and Simulation: Shift-Left and Continuous Functional Testing for Space Software
Dr. James Hui – Windriver
15.00 KEYNOTE – Ultra-Deep Submicron Technologies for European Space Sovereignty: Advancing Next-Generation Processors and System Integration
Boris Glass – European Space Agency
15.30 SILVER SPONSOR – How we accidental ended up in Space – OpenHW Foundation
Flo Wohlrab – OpenHW Group
15.40 CHAIRMAN’S FAREWELL
Sandi Habinc – Frontgrade Gaisler
15.45 – 16.00 pm
COFFEE, POSTERS & EXHIBITION
16.00 – 17.30 pm
POSTER SESSION
P1. Ensuring Security and Reliability in Space Microprocessors with Hardware-Based Techniques
Prof. Alessandro Palumbo – CentraleSupelec, IRISA, Inria
P2. A Hardware Accelerator for Secure Communications through Post Quantum Cryptography
Ambily Suresh- Silicon Austria Labs
P3. Fault-Tolerant Soft RISC-V Linux SoCs on SRAM-based FPGAs in Space
Andrew Wilson – Brigham Young University
P4. Securing Modern Satellite Architectures and Ensuring Software Integrity
Astrid Courtay – Irdeto
P5. RISC-V * N
Barry Kavanagh – O.C.E. Technology Ltd
P6. SweRISC PISCES – A Swedish RISC-V Processor in Silicon Carbide for Extreme Space Environments
Prof. Carl-Mikael Zetterling – KTH Royal Institute of Technology
P7. Porting an ECSS Qualified Flight Boot Loader Software to RISC-V Architecture
Daniel Hellström – Frontgrade Gaisler
P8. Onboard Computer Case-Study on RISC-V Core
Dr. Fernanda Kastensmidt – UFRGS University
P9. Heterogeneous Multicore Debugging of Space-Dedicated RISC-V Chips Made Easy
Kristoffer Martinsson – Nohau/Lauterbach
P10. GRAIN – Radiation-Tolerant Edge AI
Kenneth Östberg – Frontgrade Gaisler
P11. FPGA Accelerated Post-Synthesis Fault Injection for RISC-V Cores
Eike Trumann – TU Braunschweig
P12. RADLER: A Permissive Open Source Hardware Platform for Increased Autonomy
Dr. Leonidas Kosmidis – Barcelona Supercomputing Center
P13. Accelerating CCSDS121 in RISC-V with Custom Instructions
Dr. Martin Danek – daiteq s.r.o.
P14. Safety Qualification of Open Source Software
Dr. Matthias Göbel – embedded brains GmbH &Co KG
P15. EMSA5: A RISC-V Processor System for Enhanced Functional Safety in Embedded Applications
Dr. Michael Faulwaßer – Fraunhofer IPMS
P16. The RERI-Lite Error Logging Framework
Michiel Koenderink – University of Twente
P17. An Overview of Available and Upcoming RISC-V Security Mechanisms, and their Potential use in Satellite as a Service Scenarios
Nick Kossifidis – Institute of Computer Science, Foundation for Research and Technology – Hellas (FORTH)
P18. High-Performance AI/ML Inference for Space Applications on RISC-V: A Comparative Performance Analysis
Dr. Pablo Ghiglino – Klepsydra Technologies
P19. Virtual Prototyping for Space Applications – How to get custom SoCs done Fast and Correct
Pascal Pieper – DLR RY-AVS
P20. Secure Boot and Root-of-Trust for Space-Grade RISC-V Systems
Jan Andersson – Frontgrade Gaisler for Xiphera Ltd
P21. Highly Parallel Rad-Hard RISC-V-based Manycore Accelerators
Prof. Ran Ginosar – Ramon Space
P22. Fast Single Event Upset Detection Technique for Processors
Stefan De Raedemaeker – KU Leuven
P23. World’s First 50 TOPS RISC-V Modular and Upgradable AI Laptop for Advanced Space Systems Development
Yuning Liang – DeepComputing
16.00 – 17.30 pm
Master Thesis Posters
P24. MemoryBoost: RISC-V Temporal Isolation Through Dynamic Hypervisor-level Bandwidth Reservation
Afonso Oliveira – Universidade do Minho
P25. Anomaly Detection for Dependable RISC-V-based Systems in Safety-Critical Applications
Niccolò Frascarelli – Università di Pisa
P26. Development of Radiation Tolerant Data Acquisition System for a Langmuir Probe Instrument
Romina Gaudio Couselo – Kungliga Tekniska Högskolan
P27. Instrument Software Development for Langmuir Probe Onboard ROMEO Satellite
Sergiu Bogdan Popescu – Kungliga Tekniska Högskolan
P28. Coherent On-chip Architecture Evaluation for RISC-V Multi-processor
Veronica Kimelman & Alex Helmersson – Chalmers Tekniska Högskola
using WordPress and