Roger Espasa

CEO
Semidynamics

Biography

Roger Espasa got his Phd in Computer Science from Universitat Politècnica de Catalunya in 1997. Between 1999 and 2001 he worked for the Alpha Microprocessor Group on a vector extension to the Alpha architecture (see the Tarantula paper). In 2002, the Alpha team was acquired by Intel. between 2002 and 2014 Roger worked at Intel developing a vector extension for the x86 ISA which was initially deployed in the Larrabee and Knight’s Corner product and then became the AVX-512 extension. Roger also led the team implementing the texture sampling unit for the original Larrabee chip. Roger also worked on the core for the Knight’s Landing product (14nm) and led the core for the follow-on Knights Hill 10nm product. In 2014, Roger joined Broadcom where he worked on a from-scratch ARMV8 wide out-of-order core supporting both A64 and A32. In 2016 Roger founded SemiDynamics Technology Services. From 2016 to 2019, Roger was Esperanto Technologies chief architect, where he developed a 7nm architecture for machine learning. Additionally, from 2018 onward, Roger is leading the design of the Avispado RISC-V core, targeted at high-bandwidth applications and supporting an open vector interface to vector processing units. Roger has published over 40 peer-reviewed papers on Vector Architectures, Graphics/3D Architecture, Binary translation and optimization, Branch Prediction, and Media ISA Extensions. Roger holds 9 patents with 41 international filings.

All-in-one cpu, vector and tensor RISC-V computing from Semidynamics

In this talk we will describe Semidynamic’s solution for future-proof AI compute, based on the combination in a single element of Semidynamics RISC-V core, vector and tensor unit. We will cover the new tensor instructions implemented by Semidynamics, how these can be used in AI convolutions and matrix multiplication. We will also cover the need for the vector unit in many areas of computing such as networking, DSP and AI.